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0-In Introduces Breakthrough Automatic Verification of Metastability Effects
Archer Verification(TM) System Verifies Every Functional
Effect of Clock-Domain Crossing Metastability
SAN JOSE, Calif.—(BUSINESS WIRE)—May 17, 2004—
Today 0-In Design Automation, the Assertion-Based Verification
Company, announced a new product in its Archer Verification(TM) system
incorporating breakthrough technology that automates the verification
of all possible clock-domain crossing (CDC) metastability effects (FX)
in system-on-chip (SoC) and ASIC designs. This pioneering product,
named CDC-FX, gives design and verification teams a push-button
methodology for determining whether variable-length cycle delays
(jitter) of signals crossing clock domains may cause functional
defects in their register-transfer level (RTL) designs.
Today, many design teams manually enforce design styles and
methodologies to prevent functional bugs arising from metastability
effects. The CDC-FX addition to 0-In's Archer Verification system
automates this process and detects all possible metastability effect
errors, leading to more thorough verification in less time. The CDC-FX
capability is unique to 0-In and complements existing CDC verification
features in the Archer Verification system for clock synchronization
checking and CDC protocol checking.
"CDC-FX is part of our continuing effort to automate and provide
complete solutions for the most critical verification tasks facing our
customers," said Steve White, president and CEO of 0-In. "This is
another example of how the engineered combination of simulation and
exhaustive formal verification techniques yields 10x verification
productivity gains."
CDC-FX Synthesizes Generators that Intelligently Inject
Metastability Effects
CDC-FX automatically synthesizes a metastability effect generator
into a RTL description of a design. The generator introduces
metastability effects by analyzing simulation and intelligently
injecting signal errors whenever metastability may arise -- at every
clock-domain crossing in the design, whether synchronized or not. The
injected metastability errors stress the design during simulation of
the original RTL description using existing testbenches and existing
end-to-end checks which exposes functional and performance defects.
Since no additional checking specific to CDC is required, users can
start using CDC-FX with very little effort.
Formal Verification Exhaustively Analyzes Metastability Effects
As well as using CDC-FX to find functional and performance
defects, users can apply the exhaustive static and dynamic formal
verification capabilities of the Archer Verification system to the RTL
description with the metastability generator to thoroughly analyze all
possible metastability errors. Archer Verification's formal analysis
finds design bugs caused by jitter and determines the minimum amount
of jitter needed to demonstrate such bugs. The combination of
simulation, formal verification and CDC-FX reduces the time needed to
reach closure on the critical verification task of preventing
functional bugs being introduced into the design by jitter.
For further technical information, please refer to the paper,
"Formally verifying clock domain crossing jitter using assertion-based
verification," by Tai Ly, Neil Hand and Chris Kwok, published in
proceedings of the Design and Verification Conference (DVCon), March
2004.
New Archer Product Delivers Complete CDC Verification Solution
For new customers focused on solving their CDC verification
problems, the Archer Verification system has been broadened to include
Archer-CDC, a complete package that includes CDC-FX, clock
synchronization checking, CDC protocol checking (static and dynamic)
and CDC reconvergence checking. Existing customers can receive the
same capabilities by purchasing CDC-FX as an add-on to Archer-CDV.
Pricing and Availability
North American list price for Archer-CDC is $100,000; CDC-FX
add-on to the Archer-CDV product is $50,000. Archer-CDC and CDC-FX
will be demonstrated in Booth #3243 at the Design Automation
Conference (DAC) in San Diego, June 7-11, and will ship to beta
customers starting in Q3 of 2004.
About 0-In
0-In Design Automation, Inc. (pronounced "zero-in") develops and
supports functional verification products that help verify
multi-million gate application-specific integrated circuit (ASIC) and
system-on-chip (SoC) designs. The company delivers a comprehensive
assertion-based verification (ABV) solution built on industry
standards that provides value throughout the design and verification
cycle -- from the block level to the chip and system levels. Twelve of
the 15 largest electronics companies have adopted 0-In tools and
methodologies in their integrated circuit (IC) design verification
flows. 0-In was founded in 1996 and is based in San Jose, Calif. For
more information, see http://www.0-in.com.
0-In(R) and CheckerWare(R) and Archer Verification(TM) are
trademarks or registered trademarks of 0-In Design Automation, Inc.
All other trademarks are the property of their respective holders.
Contact:
0-In Design Automation
Richard Ho, 408-487-3647
richard@0-in.com
or
Cayenne Communication for 0-In Design Automation
Linda Marchant, 919-683-9545
linda.marchant@cayennecom.com
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